Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Abstract Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of were used to improve hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) Fredrick gate (MCF) Reversible Logic (BWM-MCT-MCF) will be analyzed. Initially, Full Adder (RFA) is designed gates. Then proposed Multiplier. By this, it reduces complexity with higher speed, lower area, power consumption. The BWM-MCT-MCF multiplier implemented MATLAB, its performance shows Garbage output 22.78%, 24.88%, 20.95% compared designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Xilinx ISE tool Virtex 5 device. From FPGA-BWM-MCT-MCF method delay 23.77%, 16.86% FPGA-BWM-RL-TG, FPGA-BWM-TG-FG